Non-volatile memories are widely used for storing data in computer systems, and typically include a memory array with a large number of memory cells arranged in rows and columns. In some embodiments, each of the memory cells may include at least a non-volatile element, such as charge trapping field-effect transistor (FET), floating gate transistor, that is programmed or erased by applying a voltage of the proper polarity, magnitude and duration between a control/memory gate and the substrate. For example, in a charge trapping FET, a positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer raising a threshold voltage (VT) of the transistor, and a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer lowering the threshold voltage.
Some contemporary system-on-chip integrated circuits (SOC ICs), such as micro-controllers, touch screen controllers, and smart cards have a significant amount of embedded non-volatile memory (NVM) in the form of flash and/or electrically erasable programmable read-only memory (EEPROM). Flash may be preferred in storing of data that is less frequently updated, such as for code and large data structure storage, while EEPROM may be more suitable for smaller, more frequently updated data structures. In some embodiments, charge-trapping memory technology, such as silicon-oxide-nitride-oxide-silicon (SONOS), is a fitting option for embedded NVM due to its low cost and simplicity of integration into complementary metal-oxide-silicon (CMOS) flows. SONOS has typically been adopted in a flash solution where a page (or row) may be the smallest block that is written to at a time. EEPROM operation, on the other hand, requires the capability to write to a smaller block (byte or word) at a time, and may adopt the floating gate memory technology. Due to their differences in structures and fabrication processes, flash memory (e.g. SONOS transistors) and EEPROM (e.g. floating gate transistors) memory may be disposed in separate portions on a single IC package or semiconductor die, or even in separate IC packages or dies in a system, and being operated individually.
There are demands to use one NVM technology, such as SONOS, for both flash and EEPROM schemes. The combined memory array may enable byte and word programming capabilities where a single page may be programmed up to 32 times or more. Moreover, the combined array removes the need for a separate EEPROM area on an embedded system, such as SOC. Programming a single SONOS page multiple times without erasing may cause memory bits to experience elevated levels of inhibit disturb.
It is, therefore, an object of the present invention to provide an optimized SONOS stack, doping scheme, and biasing conditions to reduce the inhibit disturb seen by these bits to the level that enables reliable word programming operation.